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Disambiguation of "Brea, Víctor M."

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CMOS-3D Smart Imager Architectures for Feature Detection.

, , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 2 (4): 723-736 (2012)

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Brea Gerson

Pádraig Breatnach

Andrea Bréard

Víctor Farías

Víctor Castaño

 

Other publications of authors with the same name

Pulsed time-of-flight pixel with on-chip 20 klux background light suppression in standard CMOS technology., , , and . Int. J. Circuit Theory Appl., 46 (5): 987-1005 (2018)Split and shift methodology on cellular processor arrays: area saving versus time penalty., , and . Int. J. Circuit Theory Appl., 42 (3): 258-295 (2014)Relating Cellular Non-linear Networks to Threshold Logic and Single Instruction Multiple Data computing models., , , , and . ECCTD, page 92-95. IEEE, (2007)Fast Time-Domain Super-Resolution for Single-Shot Multi- Path ToF Imaging., , , , and . ICECS 2022, page 1-4. IEEE, (2022)Feature detection and matching on an SIMD/MIMD hybrid embedded processor., , and . CVPR Workshops, page 21-26. IEEE Computer Society, (2012)In-pixel ADC for a vision architecture on CMOS-3D technology., , , , , and . 3DIC, page 1-7. IEEE, (2010)Pixel-Level Snakes., , , and . ICPR, page 1640-1643. IEEE Computer Society, (2000)Effect of temporal and spatial noise on the performance of hardware oriented background extraction algorithms., , , and . NEWCAS, page 45-48. IEEE, (2017)Scale- and rotation- invariant feature detectors on Cellular Processor Arrays., , , and . ISCAS, page 2657-2660. IEEE, (2012)Dynamic model of on-chip inverting capacitive charge pumps with charge reusing., , , and . ISCAS, page 1626-1629. IEEE, (2016)