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GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.

G. Dai, T. Huang, Y. Chi, J. Zhao, G. Sun, Y. Liu, Y. Wang, Y. Xie, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 640-653 (2019)

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Yang Yang

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Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.Y. Wang, H. Luo, K. He, R. Luo, H. Yang, and Y. Xie. IEEE Trans. Dependable Secur. Comput., 8 (5): 756-769 (2011)Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication.L. Xia, P. Gu, B. Li, T. Tang, X. Yin, W. Huangfu, S. Yu, Y. Cao, Y. Wang, and H. Yang. J. Comput. Sci. Technol., 31 (1): 3-19 (2016)Low-Cost Multi-Agent Navigation via Reinforcement Learning With Multi-Fidelity Simulator.J. Qiu, C. Yu, W. Liu, T. Yang, J. Yu, Y. Wang, and H. Yang. IEEE Access, (2021)A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed.Z. Wang, Y. Liu, A. Lee, F. Su, C. Lo, Z. Yuan, J. Li, C. Lin, W. Chen, H. Chiu and 7 other author(s). IEEE J. Solid State Circuits, 52 (10): 2769-2785 (2017)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility.Y. Chen, M. Lee, G. Dai, M. Zhou, N. Challapalle, T. Wang, Y. Yu, Y. Liu, Y. Wang, H. Yang and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)Active Neural Topological Mapping for Multi-Agent Exploration.X. Yang, Y. Yang, C. Yu, J. Chen, J. Yu, H. Ren, H. Yang, and Y. Wang. IEEE Robotics Autom. Lett., 9 (1): 303-310 (January 2024)INCAME: Interruptible CNN Accelerator for Multirobot Exploration.J. Yu, Z. Xu, S. Zeng, C. Yu, J. Qiu, Z. Shen, Y. Xu, G. Dai, Y. Wang, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (4): 964-978 (2022)GAAS: An Efficient Group Associated Architecture and Scheduler Module for Sparse CNN Accelerators.J. Wang, Z. Yuan, R. Liu, X. Feng, L. Du, H. Yang, and Y. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5170-5182 (2020)Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms.Q. Zhao, W. Sun, J. Zhao, J. Zhao, H. Yao, T. Ho, X. Guo, H. Yang, and Y. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (11): 2043-2057 (2019)ULSeq-TA: Ultra-Long Sequence Attention Fusion Transformer Accelerator Supporting Grouped Sparse Softmax and Dual-Path Sparse LayerNorm.J. Wang, L. Zhang, X. Li, H. Yang, and Y. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (3): 892-905 (March 2024)

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Disambiguation of "Yang, Huazhong"

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GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yang, Huazhong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.

Please choose a person to relate this publication to

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Yang Yang

Other publications of authors with the same name

Disambiguation

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GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.