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Optimizing Memory Throughput In a Tightly Coupled Multiprocessor., and . ICPP, page 344-346. Pennsylvania State University Press, (1987)HAVEGE: A user-level software heuristic for generating empirically strong random numbers., and . ACM Trans. Model. Comput. Simul., 13 (4): 334-346 (2003)Fetch Gating Control through Speculative Instruction Window Weighting., and . Trans. High Perform. Embed. Archit. Compil., (2009)Topic 08+13: Instruction-Level Parallelism and Computer Architecture., , , , , , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 385. Springer, (2001)Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments., and . J. Parallel Distributed Comput., 3 (4): 508-526 (1986)Fetch Gating Control Through Speculative Instruction Window Weighting., and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 120-135. Springer, (2007)DITVA: Dynamic Inter-Thread Vectorization Architecture., , , and . J. Parallel Distributed Comput., (2018)On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE., , and . ACM Trans. Archit. Code Optim., 14 (2): 18:1-18:24 (2017)The inner most loop iteration counter: a new dimension in branch history., , and . MICRO, page 347-357. ACM, (2015)Effective ahead Pipelining of Instruction Block Address Generation., and . ISCA, page 241-252. IEEE Computer Society, (2003)