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DRPM: dynamic speed control for power management in server class disks, , , and . SIGARCH Comput. Archit. News, 31 (2): 169--181 (2003)A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads., , , , , , , , , and 1 other author(s). ISSCC, page 104-105. IEEE, (2010)Disaggregated and optically interconnected memory: when will it be cost effective?, , , , and . CoRR, (2015)Introduction to the wire-speed processor and architecture., , , , , , and . IBM J. Res. Dev., 54 (1): 3 (2010)Toward performance optimization with CPU offloading for virtualized multi-tenant data center networks., , , and . IEEE Netw., 30 (3): 59-63 (2016)Decentralized management for transportation-logistics: A multi agent based approach., and . Integr. Comput. Aided Eng., 10 (2): 203-210 (2003)A taxonomy of accelerator architectures and their programming models., , , , and . IBM J. Res. Dev., 54 (5): 5 (2010)Dynamic atomicity: optimizing swift memory management., , and . DLS, page 15-26. ACM, (2017)Model-Integrated Program Synthesis Environment., , and . ECBS, page 348-355. IEEE Computer Society, (1996)DeepStore: In-Storage Acceleration for Intelligent Queries., , , , , , , , , and . MICRO, page 224-238. ACM, (2019)