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System Level Energy Optimization for Location Aware Computing.

, , and . PerCom, page 319-323. IEEE Computer Society, (2005)

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On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs., and . ISQED, page 33-39. IEEE Computer Society, (2009)Simultaneous Scheduling, Allocation, Binding, Re-ordering, and Encoding for Crosstalk Pattern Minimization during High Level Synthesis., and . ISVLSI, page 423-428. IEEE Computer Society, (2008)A customizable FPGA IP core implementation of a general purpose Genetic Algorithm engine., , , , , , and . IPDPS, page 1-8. IEEE, (2008)Self-Reconfigurable Mixed-Signal Integrated Circuits Architecture Comprising a Field Programmable Analog Array and a General Purpose Genetic Algorithm IP Core., , , , , , , and . ICES, volume 5216 of Lecture Notes in Computer Science, page 225-236. Springer, (2008)Simultaneous Scheduling, Allocation, Binding, Re-Ordering, and Encoding for Crosstalk Pattern Minimization During High-Level Synthesis., and . IEEE Trans. Very Large Scale Integr. Syst., 19 (2): 217-226 (2011)High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs.. University of South Florida, Tampa, USA, (2008)base-search.net (ftunisfloridatam:oai:digitalcommons.usf.edu:etd-1486).Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs., , and . VLSI Design, page 463-468. IEEE Computer Society, (2005)Self-Reconfigurable Analog Array Integrated Circuit Architecture for Space Applications., , , , , , , and . AHS, page 83-90. IEEE Computer Society, (2008)Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis., and . DELTA, page 454-457. IEEE Computer Society, (2008)Floorplan Driven High Level Synthesis for Crosstalk Noise Minimization in Macro-cell Based Designs., and . ISVLSI, page 274-279. IEEE Computer Society, (2009)