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Disambiguation of "Chandramouli, V."

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A new, precharged, low-power logic family for GaAs circuits.

, , and . IEEE J. Solid State Circuits, 30 (2): 140-143 (February 1995)

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Badrish Chandramouli

Krishna Chandramouli

Chandramouli Chillakuri

V Saile

V Geoffroy

 

Other publications of authors with the same name

Self-Timed Design in GaAs - Case Study of a High-Speed, Parallel Multiplier., , and . IEEE Trans. Very Large Scale Integr. Syst., 4 (1): 146 (1996)A new, precharged, low-power logic family for GaAs circuits., , and . IEEE J. Solid State Circuits, 30 (2): 140-143 (February 1995)AFTA: A Formal Delay Model for Functional Timing Analysis., , and . DATE, page 350-355. IEEE Computer Society, (1998)Delay modeling for functional timing analysis.. University of Michigan, USA, (1998)Including inductive effects in interconnect timing analysis., , and . CICC, page 445-452. IEEE, (1999)Modeling the Effects of Temporal Proximity of Input Transitions on Gate Propagation Delay and Transition Time., and . DAC, page 617-622. ACM Press, (1996)An Integrated Technology CAD System for Process and Device Designers., , , , , and . VLSI Design, page 287-292. IEEE Computer Society, (1993)Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity., , and . ARVLSI, page 32-46. IEEE Computer Society, (1997)Bridging faults and their implication to PLAs., , , and . ITC, page 852-859. IEEE Computer Society, (1990)A realizable driving point model for on-chip interconnect with inductance., and . DAC, page 190-195. ACM, (2000)