( en | de | ru )

 

Disambiguation of "Mishchenko, Alan"

Author of the publication

copydeleteadd this publication to your clipboard
Linear cofactor relationships in Boolean functions.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 1011-1023 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Oleksiy Mishchenko

Maia Alandjiyska

Safwat Alani

Yilmaz Alan

Bertold Aland

 

Other publications of authors with the same name

Invariant-Strengthened Elimination of Dependent State Elements., , , , and . FMCAD, page 1-9. IEEE, (2008)NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract)., , , , , , and . BCB, page 623-624. ACM, (2014)Scalable min-register retiming under timing and initializability constraints., , and . DAC, page 534-539. ACM, (2008)A theory of nondeterministic networks., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (6): 977-999 (2006)Improvements to Technology Mapping for LUT-Based FPGAs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (2): 240-253 (2007)m-Inductive Property of Sequential Circuits., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (6): 919-930 (2016)Effective Logic Synthesis for Threshold Logic Circuit Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (5): 926-937 (2019)Fast computation of symmetries in Boolean functions.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (11): 1588-1593 (2003)Incremental ATPG methods for multiple faults under multiple fault models., , , and . ISQED, page 177-180. IEEE, (2015)Three-Input Gates for Logic Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)