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Exploiting the DRAM Microarchitecture to Increase Memory-Level Parallelism., , , , and . CoRR, (2018)Reducing DRAM Refresh Overheads with Refresh-Access Parallelism., , , , , , and . CoRR, (2018)Improved performance of a low-cost PDR system through sensor calibration and analysis., , , and . AIM, page 1747-1752. IEEE, (2014)A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM., , , , and . IEEE Comput. Archit. Lett., 16 (2): 88-93 (2017)DTN-SMTP: A Novel Mail Transfer Protocol with Minimized Interactions for Space Internet., , , , and . ICCSA (1), volume 12249 of Lecture Notes in Computer Science, page 322-331. Springer, (2020)GRIM-Filter: Fast Seed Location Filtering in DNA Read Mapping Using Processing-in-Memory Technologies., , , , , , , , , and . CoRR, (2017)A case for exploiting subarray-level parallelism (SALP) in DRAM., , , , and . ISCA, page 368-379. IEEE Computer Society, (2012)Tiered-latency DRAM: A low latency and low cost DRAM architecture., , , , , and . HPCA, page 615-626. IEEE Computer Society, (2013)Architecting an Energy-Efficient DRAM System for GPUs., , , , , , and . HPCA, page 73-84. IEEE Computer Society, (2017)Saving PAM4 Bus Energy with SMOREs: Sparse Multi-level Opportunistic Restricted Encodings., , , , and . HPCA, page 1001-1013. IEEE, (2022)