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AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance.

, , , , and . PACT, page 367-378. IEEE Computer Society, (2015)

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StatTask: reuse distance analysis for task-based applications., , and . RAPIDO@HiPEAC, page 1:1-1:7. ACM, (2015)An Energy-Efficient Processor Architecture for Embedded Systems., , , , and . IEEE Comput. Archit. Lett., 7 (1): 29-32 (2008)Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors., , , and . HPCA, page 424-434. IEEE, (2020)TaskInsight: Understanding Task Schedules Effects on Memory and Performance., , , and . PMAM@PPoPP, page 11-20. ACM, (2017)Register pointer architecture for efficient embedded processors., , , , , and . DATE, page 600-605. EDA Consortium, San Jose, CA, USA, (2007)Every walk's a hit: making page walks single-access cache hits., , , and . ASPLOS, page 128-141. ACM, (2022)Modeling and optimizing NUMA effects and prefetching with machine learning., , , , , and . ICS, page 34:1-34:13. ACM, (2020)Understanding the interplay between task scheduling, memory and performance., , and . SPLASH (Companion Volume), page 21-23. ACM, (2017)Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit., , , and . J. Signal Process. Syst., 91 (3-4): 379-397 (2019)Filter caching for free: the untapped potential of the store-buffer., , , and . ISCA, page 436-448. ACM, (2019)