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Disambiguation of ""Nunez-Yanez, Jose Luis""

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Optimised OpenCL Workgroup Synthesis for Hybrid ARM-FPGA Devices

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Biologically compatible neural networks with reconfigurable hardware., , and . Microprocess. Microsystems, 39 (8): 693-703 (2015)A toolset for the analysis and optimization of motion estimation algorithms and processors., , and . FPL, page 423-428. IEEE, (2009)CPCIe: A compression-enabled PCIe core for energy and performance optimization., and . NORCAS, page 1-6. IEEE, (2016)Run-time power gating in hybrid ARM-FPGA devices., and . FPL, page 1-6. IEEE, (2014)Evaluation of Early-exit Strategies in Low-cost FPGA-based Binarized Neural Networks., , and . DSD, page 1-8. IEEE, (2022)Energy Optimization in Commercial FPGAs with Voltage, Frequency and Logic Scaling., , and . IEEE Trans. Computers, 65 (5): 1484-1493 (2016)Numerically efficient and biophysically accurate neuroprocessing platform., , and . ReConFig, page 1-6. IEEE, (2013)Entropy-Based Early-Exit in a FPGA-Based Low-Precision Neural Network., and . ARC, volume 13569 of Lecture Notes in Computer Science, page 72-86. Springer, (2022)Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform., and . ACM Trans. Reconfigurable Technol. Syst., 5 (4): 20:1-20:22 (2012)Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices., and . FPL, page 1-6. IEEE, (2015)