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An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation., , , and . ISCAS, page 1-4. IEEE, (2017)All-hardware SIFT implementation for real-time VGA images feature extraction., , , , , , and . J. Real Time Image Process., 17 (2): 371-382 (2020)VHDL-AMS modeling of self-organizing neural systems., and . ISCAS, page 734-737. IEEE, (2000)A fourth order CMOS band pass filter for PIR sensors., , , , , , , , , and . ICECS, page 268-271. IEEE, (2012)Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem., , , and . FPL, page 1-5. IEEE, (2006)An all-hardware implementation of the subpixel refinement stage in SIFT algorithm., , , , , , and . Int. J. Circuit Theory Appl., 46 (9): 1690-1702 (2018)Description and Simulation of Bio-inspired Systems Using VHDL-AMS., , and . IWINAC (2), volume 3562 of Lecture Notes in Computer Science, page 357-365. Springer, (2005)An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks., , , and . IWANN (2), volume 2687 of Lecture Notes in Computer Science, page 97-104. Springer, (2003)