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Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity.

, and . FPGA, page 187. ACM, (2019)

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Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector Multiplication on FPGA with Subquadratic Space Complexity., and . FPGA, page 187. ACM, (2019)FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures., , and . Microelectron. J., 41 (6): 365-370 (2010)FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^m)$ and Their Applications in Trinomial Multipliers., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 725-734 (2017)Low-latency area-delay-efficient systolic multiplier over GF(2m) for a wider class of trinomials using parallel register sharing., , and . ISCAS, page 89-92. IEEE, (2012)Hardware Efficient Approach for Memoryless-Based Multiplication and Its Application to FIR Filter., and . J. Comput., 6 (11): 2376-2381 (2011)Low-Complexity Systolic Multiplier for GF(2m) using Toeplitz Matrix-Vector Product Method., , and . ISCAS, page 1-5. IEEE, (2019)Reliable Inversion in GF(28) With Redundant Arithmetic for Secure Error Detection of Cryptographic Architectures., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (3): 696-704 (2018)Efficient Hardware Implementation of Finite Field Arithmetic $AB+C$AB+C for Binary Ring-LWE Based Post-Quantum Cryptography., , , and . IEEE Trans. Emerg. Top. Comput., 10 (2): 1222-1228 (2022)Novel Low-Complexity Polynomial Multiplication Over Hybrid Fields for Efficient Implementation of Binary Ring-LWE Post-Quantum Cryptography., , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 383-394 (2021)High-Performance Polynomial Multiplication Hardware Accelerators for KEM Saber and NTRU., , and . IACR Cryptol. ePrint Arch., (2022)