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Disambiguation of "Tanaka, Hitoshi"

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Advanced Machine Learning Techniques for Predicting Nha Trang Shorelines.

, , , , , , , , , , , and . IEEE Access, (2021)

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Masao Tanaka

Hitoshi Tamura

Masafumi Tanaka

Hitoshi Endo

Hitoshi Abe

 

Other publications of authors with the same name

Estimating damage-mitigation level of collision-prevention support braking., , , and . Intelligent Vehicles Symposium, page 648-653. IEEE, (2011)Dynamic analysis of innovation and international transfer of technology through licensing, , and . Journal of International Economics, 73 (1): 189--212 (September 2007)A remark on two generalized Orlicz-Morrey spaces., , and . J. Approx. Theory, (2015)Using Hybrid Wavelet-Exponential Smoothing Approach for Streamflow Modeling., , , and . Complex., (2021)An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture., , , , , , , , , and 11 other author(s). IEEE J. Solid State Circuits, 30 (11): 1165-1173 (November 1995)Visualization of large-scale internal seiche in Lake Inawashiro., , and . J. Vis., 6 (1): 4 (2003)Sub-1-μA dynamic reference voltage generator for battery-operated DRAMs., , , , , and . IEEE J. Solid State Circuits, 29 (4): 448-453 (April 1994)Deep Learning-enabled Detection and Classification of Bacterial Colonies using a Thin Film Transistor (TFT) Image Sensor., , , , , , , , , and 2 other author(s). CoRR, (2022)Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications., , , , and . IEICE Trans. Electron., 88-C (4): 608-613 (2005)An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 42 (1): 201-209 (2007)