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Reducing control overhead in dataflow architectures., , , , , , and . PACT, page 182-191. ACM, (2006)How to implement effective prediction and forwarding for fusable dynamic multicore architectures., , , , , , , and . HPCA, page 460-471. IEEE Computer Society, (2013)Instruction scheduling for a tiled dataflow architecture., , , , , , and . ASPLOS, page 141-150. ACM, (2006)The WaveScalar architecture., , , , , , , and . ACM Trans. Comput. Syst., 25 (2): 4:1-4:54 (2007)CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures., , , , and . FPGA, page 261. ACM, (2008)MPI as an abstraction for software-hardware interaction for HPRCs., , , , , , , , and . HPRCTA@SC, page 1-10. IEEE, (2008)What To Do With Datacenter FPGAs Besides Deep Learning.. FPGA, page 26. ACM, (2020)KV-Direct: High-Performance In-Memory Key-Value Store with Programmable NIC., , , , , , , and . SOSP, page 137-152. ACM, (2017)Modeling instruction placement on a spatial architecture., , , , , , and . SPAA, page 158-169. ACM, (2006)CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures., , , , , and . FPL, page 173-178. IEEE, (2008)