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A Power Efficient SAR Algorithm for High Resolution ADCs., , , , , , and . ISCAS, page 1-5. IEEE, (2018)Power Optimized Comparator Selecting Method For Stochastic ADC., , , , , , and . ISCAS, page 1-4. IEEE, (2018)Digital techniques for improving the accuracy of data converters., , and . IEEE Communications Magazine, 37 (10): 136-143 (1999)Analysis of back-end flash in a 1.5b/stage pipelined ADC., , and . ISCAS, page 2247-2250. IEEE, (2013)Class A+ amplifier with controlled positive feedback for discrete-time signal processing circuits., , , and . ISCAS, page 428-431. IEEE, (2012)Correlated jitter sampling for jitter cancellation in pipelined TDC., , , and . ISCAS, page 810-813. IEEE, (2012)A 71dB dynamic range third-order ΔΣ TDC using charge-pump., , , and . VLSIC, page 168-169. IEEE, (2012)A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier., , , , and . VLSIC, page 1-2. IEEE, (2014)An improved algorithmic ADC clocking scheme., , and . ISCAS (1), page 589-592. IEEE, (2004)Jitter in high-speed serial and parallel links., , , , and . ISCAS (4), page 425-428. IEEE, (2004)