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Automatic generation of loop scheduling for VLIW., , , and . PACT, page 306-309. IFIP Working Group on Algol / ACM, (1995)Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-Offs., , , and . International Conference on Supercomputing, page 12-19. ACM, (1997)Memory Access Synchronization in Vector Multiprocessors., , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 414-425. Springer, (1994)Parallel Computer Architecture., , , and . Euro-Par, volume 1900 of Lecture Notes in Computer Science, page 537-538. Springer, (2000)Topic 15+20: Multimedia and Embedded Systems., , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 651-652. Springer, (2001)Improved spill code generation for software pipelined loops., , , and . PLDI, page 134-144. ACM, (2000)The Ultimate DataFlow for Ultimate SuperComputers-on-a-Chip, for Scientific Computing, Geo Physics, Complex Mathematics, and Information Processing., , , , , , , , , and 10 other author(s). MECO, page 1-6. IEEE, (2021)EcoTM: Conflict-Aware Economical Unbounded Hardware Transactional Memory., , , , and . ICCS, volume 18 of Procedia Computer Science, page 270-279. Elsevier, (2013)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , and . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)