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Disambiguation of "Yoshioka, Shinichi"

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A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU.

, , , , , , , , , , , , and . IEEE J. Solid State Circuits, 44 (1): 83-89 (2009)

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Riohei Yoshioka

Shinichi Kotabe

 

Other publications of authors with the same name

SH3: high code density, low power., , , , , and . IEEE Micro, 15 (6): 11-19 (1995)A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 44 (1): 83-89 (2009)A 0.9-V, 150-MHz, 10-mW, 4 mm2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 31 (11): 1770-1779 (1996)A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management., , , , , , , and . ASP-DAC, page 535-539. IEEE, (2009)SH-MobileG1: A single-chip application and dual-mode baseband processor., , , , , , , , , and 3 other author(s). Hot Chips Symposium, page 1-24. IEEE, (2006)A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU., , , , , , , , , and 3 other author(s). ISSCC, page 260-261. IEEE, (2008)A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS., , , , , , , , , and 2 other author(s). ISSCC, page 274-602. IEEE, (2007)A 342mW mobile application processor with full-HD multi-standard video codec., , , , , , , , , and 4 other author(s). ISSCC, page 158-159. IEEE, (2009)A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor., , , , , , , , , and 14 other author(s). ISSCC, page 2210-2219. IEEE, (2006)Hierarchical power distribution and power management scheme for a single chip mobile processor., , , , , , , , , and 23 other author(s). DAC, page 292-295. ACM, (2006)