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A Reconfigurable Architecture with Sequential Logic-Based Stochastic Computing.

, , , , , and . JETC, 13 (4): 57:1-57:28 (2017)

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Parallel implementation of finite state machines for reducing the latency of stochastic computing., and . ISQED, page 335-340. IEEE, (2018)Cost-quality trade-offs of approximate memory repair mechanisms for image data., , and . ISQED, page 438-444. IEEE, (2017)Design of a spintronic arithmetic and logic unit using magnetic tunnel junctions., , , , and . Conf. Computing Frontiers, page 171-178. ACM, (2008)Performing bitwise logic operations in cache using spintronics-based magnetic tunnel junctions., and . Conf. Computing Frontiers, page 33. ACM, (2011)Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions., , and . Euro-Par, volume 2400 of Lecture Notes in Computer Science, page 468-480. Springer, (2002)Increasing Instruction-Level Parallelism with Instruction Precomputation (Research Note)., , and . Euro-Par, volume 2400 of Lecture Notes in Computer Science, page 481-485. Springer, (2002)A Stepwise Approach to Software-Hardware Performance Co-optimization Using Design of Experiments., , , and . Int. CMG Conference, Computer Measurement Group, (2013)Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic., , and . ACM Great Lakes Symposium on VLSI, page 208-211. ACM, (2007)Performance Analysis and Prediction of Processor Scheduling Strategies in Multiprogrammed Shared-Memory Multiprocessors., and . ICPP, Vol. 3, page 70-78. IEEE Computer Society, (1996)0-8186-7623-X.Energy-Efficient Pulse-Based Convolution for Near-Sensor Processing., , , and . ISCAS, page 1-5. IEEE, (2020)