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Другие публикации лиц с тем же именем

Combinational equivalence checking for threshold logic circuits., , и . ACM Great Lakes Symposium on VLSI, стр. 102-107. ACM, (2007)Power Reduction of Functional Units Considering Temperature and Process Variations., , , и . VLSI Design, стр. 533-539. IEEE Computer Society, (2008)Temperature and Process Variations Aware Power Gating of Functional Units., , , , и . VLSI Design, стр. 515-520. IEEE Computer Society, (2008)Statistical library characterization using arbitrary polynomial chaos., , и . LASCAS, стр. 1-4. IEEE, (2017)A fast, energy efficient, field programmable threshold-logic array., , и . FPT, стр. 300-305. IEEE, (2014)Technology-design co-optimization of resistive cross-point array for accelerating learning algorithms on chip., , , , , , , , , и . DATE, стр. 854-859. ACM, (2015)REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs)., , и . DAC, стр. 18:1-18:10. ACM, (2013)Branch-Aware Loop Mapping on CGRAs., , и . DAC, стр. 107:1-107:6. ACM, (2014)Statistical Timing Analysis Using Bounds., , , и . DATE, стр. 10062-10067. IEEE Computer Society, (2003)Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series., и . DSD, стр. 139-143. IEEE Computer Society, (2005)