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Disambiguation of "Makino, Hiroshi"

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A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die.

, , , , , , , , , , , , , , , , and . ISSCC, page 488-617. IEEE, (2007)

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Hiroshi Kawabe

Hiroshi Murata

Hiroshi Kubota

Hiroshi Uchida

Hiroshi Fukuzaki

 

Other publications of authors with the same name

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology., , , , , and . ISLPED, page 15-20. ACM, (2008)A 32×24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure., , , , , and . ISCAS (1), page 73-76. IEEE, (2005)Energy dissipation reduction during adiabatic charging and discharging with controlled inductor current., , , , and . MWSCAS, page 1068-1071. IEEE, (2012)General Stability of Stepwise Waveform of an Adiabatic Charge Recycling Circuit With Any Circuit Topology., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (10): 2301-2314 (2012)A low power SRAM using auto-backgate-controlled MT-CMOS., , , , , , , and . ISLPED, page 293-298. ACM, (1998)The LSI implementation of a memory based field programmable device for MCU peripherals., , , , , , and . DDECS, page 183-188. IEEE Computer Society, (2014)Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability., , , , , , , , and . ICCAD, page 398-405. IEEE Computer Society, (2005)A Floating Point Divider using Redundant Binary Circuits and an Asynchronous Clock Scheme., , , and . ICCD, page 685-689. IEEE Computer Society, (1997)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 43 (1): 180-191 (2008)A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 43 (1): 96-108 (2008)