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A Concept for an Evaluation Framework for Reconfigurable Systems., and . FPL, volume 1673 of Lecture Notes in Computer Science, page 475-480. Springer, (1999)Gestaltung und Simulation hardware-rekonfigurierbarer Rechnersysteme.. GI Jahrestagung, page 239-246. Springer, (1999)Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays., , and . FPL, volume 1482 of Lecture Notes in Computer Science, page 411-415. Springer, (1998)Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms., and . FPL, volume 2778 of Lecture Notes in Computer Science, page 1119-1122. Springer, (2003)Processor design using a functional hardware description language., and . Microprocess. Microsystems, 36 (8): 676-694 (2012)Power-efficient layered turbo decoder processor., , , , , , and . DATE, page 246-251. IEEE Computer Society, (2001)