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Disambiguation of "Chiang, Patrick"

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Sinusoidal Clock Sampling for Multigigahertz ADCs.

, , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (12): 2808-2815 (2011)

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Chiang Liang

Chiang Mai

Joanna Chiang

Hsin-yi Chiang

Ming-Chiang Chung

 

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Synctium: a Near-Threshold Stream Processor for Energy-Constrained Parallel Applications., , , and . IEEE Comput. Archit. Lett., 9 (1): 21-24 (2010)0.56 V, -20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop., , , and . IEEE J. Solid State Circuits, 49 (6): 1345-1355 (2014)FotonNet: A Hardware-efficient Object Detection System using 3D-depth Segmentation and 2D-deep Neural Network Classifier., , , and . ICPRAM, page 461-468. SCITEPRESS, (2020)Sinusoidal Clock Sampling for Multigigahertz ADCs., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (12): 2808-2815 (2011)Area-constrained wirelessly-powered UWB SoC design for small insect localization., , , and . WiSNet, page 18-20. IEEE, (2016)A 2KSPS 123dB Dynamic-Range SPAD-based Optical Sensor SoC with On-chip Auto-Gain-Control and FFT Processor for 100 μlux Light Illuminance and Flicker Detection., , , , , , , , , and 2 other author(s). ISCAS, page 1-5. IEEE, (2023)A 32Gb/s NRZ, 25GBaud/s PAM4 reconfigurable, Si-Photonic MZM transmitter in CMOS., , , , , , and . OFC, page 1-3. IEEE, (2016)Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine., , , , , , and . ITC, page 1-10. IEEE, (2015)A 10Gb/s Wire-line Transceiver with Half Rate Period Calibration CDR., , , , and . ISCAS, page 1827-1830. IEEE, (2009)Energy-efficient bio-sensing systems., and . CICC, page 1. IEEE, (2014)