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Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis., , and . IOLTS, page 232-235. IEEE, (2018)Fixed Point Data Type Modeling for High Level Synthesis., , , , and . IEICE Trans. Electron., 93-C (3): 361-368 (2010)Precision tunable RTL macro-modelling cycle-accurate power estimation., and . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)S2CBench: Synthesizable SystemC Benchmark Suite for High-Level Synthesis., and . IEEE Embed. Syst. Lett., 6 (3): 53-56 (2014)Efficient Functional Locking of Behavioral IPs., and . MWSCAS, page 639-642. IEEE, (2020)Semi-Automatic Control Unit Generation for Complex VLSI Designs., and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs., and . FPT, page 193-196. IEEE, (2016)Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations., and . ICCD, page 524-531. IEEE, (2019)Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models., and . ICCAD, page 1-8. ACM, (2019)Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies.. ACM Trans. Design Autom. Electr. Syst., 22 (4): 65:1-65:20 (2017)