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Disambiguation of "Hsiao, Michael S."

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Cognitive Radio and Networking Research at Virginia Tech.

, , , , , , , , , , , , and . Proc. IEEE, 97 (4): 660-688 (2009)

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Chi-Yuan Hsiao

Lojen Hsiao

Kaijen Hsiao

Chien Hsiao

Michael Kai Mikai Hsiao

 

Other publications of authors with the same name

Fast Static Compaction Algorithms for Sequential Circuit Test Vectors., , and . IEEE Trans. Computers, 48 (3): 311-322 (1999)Multiplexed trace signal selection using non-trivial implication-based correlation., and . ISQED, page 697-704. IEEE, (2010)Efficient techniques for transition testing., , , and . ACM Trans. Design Autom. Electr. Syst., 10 (2): 258-278 (2005)A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults., , and . ACM Great Lakes Symposium on VLSI, page 455-458. ACM, (2017)SAT-based equivalence checking of threshold logic designs for nanotechnologies., , and . ACM Great Lakes Symposium on VLSI, page 225-230. ACM, (2008)Branch guided functional test generation at the RTL., , and . ETS, page 1-6. IEEE, (2015)Cognitive Radio and Networking Research at Virginia Tech., , , , , , , , , and 3 other author(s). Proc. IEEE, 97 (4): 660-688 (2009)Bilateral Testing of Nano-scale Fault-Tolerant Circuits., and . J. Electron. Test., 24 (1-3): 285-296 (2008)Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits., and . J. Electron. Test., 16 (4): 329-338 (2000)Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (3): 239-254 (1998)