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Formal verification-driven parallelisation synthesis.. University of Cambridge, UK, (2018)British Library, EThOS.An enhancement of futures runtime in presence of cache memory hierarchy., and . ITI, page 925-930. IEEE, (2008)AsmL Specification and Verification of Lamport's Bakery Algorithm.. J. Comput. Inf. Technol., 13 (4): 313-319 (2005)Sigma*: symbolic learning of input-output specifications., and . POPL, page 443-456. ACM, (2013)Verification of Causality Requirements in Java Memory Model Is Undecidable., , and . PPAM (2), volume 6068 of Lecture Notes in Computer Science, page 62-67. Springer, (2009)