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Disambiguation of "Mohanram, Kartik"

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Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience.

, , , and . IEEE Trans. Computers, 63 (2): 497-509 (2014)

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Kartik Jain

Kartik Krishnan

Kartik Viswanathan

Kartik Chandra Mondal

 

Other publications of authors with the same name

Timing-driven optimization using lookahead logic circuits., and . DAC, page 390-395. ACM, (2009)CASTLE: compression architecture for secure low latency, low energy, high endurance NVMs., and . DAC, page 87:1-87:6. ACM, (2018)WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory., , and . IEEE Trans. Computers, 65 (4): 1025-1040 (2016)Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis., , and . DATE, page 622-627. IEEE, (2009)Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification., , and . DATE, page 1490-1493. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Lowering power consumption in concurrent checkers via input ordering., and . IEEE Trans. Very Large Scale Integr. Syst., 12 (11): 1234-1243 (2004)LEO: Low Overhead Encryption ORAM for Non-Volatile Memories., and . IEEE Comput. Archit. Lett., 17 (2): 100-104 (2018)ECS: Error-Correcting Strings for Lifetime Improvements in Nonvolatile Memories., , and . ACM Trans. Archit. Code Optim., 14 (4): 40:1-40:29 (2017)CompEx: Compression-expansion coding for energy, latency, and lifetime improvements in MLC/TLC NVM., and . HPCA, page 90-101. IEEE Computer Society, (2016)ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main Memories., and . ICCD, page 100-107. IEEE Computer Society, (2018)