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Writeback-aware partitioning and replacement for last-level caches in phase change main memory systems.

, , , , and . ACM Trans. Archit. Code Optim., 8 (4): 53:1-53:21 (2012)

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Preface., and . Comput. Lang. Syst. Struct., 34 (4): 151-152 (2008)Artifact Evaluation: Is It a Real Incentive?, and . eScience, page 488-489. IEEE Computer Society, (2017)A quantitative evaluation of unified memory in GPUs., , , , and . J. Supercomput., 76 (4): 2958-2985 (2020)Implications of Memory Interference for Composed HPC Applications., , , and . MEMSYS, page 95-97. ACM, (2015)COMeT+: Continuous Online Memory Testing with Multi-Threading Extension., , and . IEEE Trans. Computers, 63 (7): 1668-1681 (2014)Detecting bugs in register allocation., , and . ACM Trans. Program. Lang. Syst., 32 (4): 15:1-15:36 (2010)Heterogeneous code cache: using scratchpad and main memory in dynamic binary translators., and . DAC, page 744-749. ACM, (2009)Tdb: a source-level debugger for dynamically translated programs., , and . AADEBUG, page 123-132. ACM, (2005)MCP: An Energy-Efficient Code Distribution Protocol for Multi-Application WSNs., , and . DCOSS, volume 5516 of Lecture Notes in Computer Science, page 259-272. Springer, (2009)Catching and Identifying Bugs in Register Allocation., , and . SAS, volume 4134 of Lecture Notes in Computer Science, page 281-300. Springer, (2006)