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A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction., , , , , , , , , и 20 other автор(ы). IEEE J. Solid State Circuits, 46 (1): 107-118 (2011)A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction., , , , , , , , , и 20 other автор(ы). ISSCC, стр. 434-435. IEEE, (2010)QE BERT: Bilingual BERT Using Multi-task Learning for Neural Quality Estimation., , , и . WMT (3), стр. 85-89. Association for Computational Linguistics, (2019)A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory., , , , , , , , , и 20 other автор(ы). IEEE J. Solid State Circuits, 53 (1): 124-133 (2018)The Effect of Presentation on Visual Working Memory., , и . HCI (26), том 434 из Communications in Computer and Information Science, стр. 346-350. Springer, (2014)Genome sequence of the hot pepper provides insights into the evolution of pungency in Capsicum species, , , , , , , , , и 61 other автор(ы). Nat. Genet., (2014)Video Indexing and Retrieval using the Cauchy Function and the Modified Hausdorff Distance., , и . SIP, стр. 309-314. IASTED/ACTA Press, (2003)An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion., , , , , , , , , и 19 other автор(ы). ISSCC, стр. 492-617. IEEE, (2007)An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion., , , , , , , , , и 14 other автор(ы). IEEE J. Solid State Circuits, 43 (1): 121-131 (2008)Design and implementation of a standards-based interoperable clinical decision support architecture in the context of the Korean EHR., , , , и . Int. J. Medical Informatics, 79 (9): 611-622 (2010)