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Disambiguation of "Choi, Haerang"

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Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics.

, , , , , , and . CoRR, (2023)

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Andreas Choi

Chiwon Choi

Bongkyung Choi

Jinsub Choi

Carmen Choi

 

Other publications of authors with the same name

System Architecture and Software Stack for GDDR6-AiM., , , , , , , , , and 31 other author(s). HCS, page 1-25. IEEE, (2022)Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation., , , and . Microprocess. Microsystems, (2020)A Novel In-DRAM Accelerator Architecture for Binary Neural Network., , , and . COOL CHIPS, page 1-3. IEEE, (2020)A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application., , , , , , , , , and 27 other author(s). IEEE J. Solid State Circuits, 58 (1): 291-302 (2023)Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics., , , , , , and . CoRR, (2023)McDRAM v2: In-Dynamic Random Access Memory Systolic Array Accelerator to Address the Large Model Problem in Deep Neural Networks on the Edge., , , , and . IEEE Access, (2020)Memory-Centric Computing with SK Hynix's Domain-Specific Memory., , , , , , , , , and 17 other author(s). HCS, page 1-26. IEEE, (2023)A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications., , , , , , , , , and 21 other author(s). ISSCC, page 1-3. IEEE, (2022)25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector., , , , , , , , , and 13 other author(s). ISSCC, page 434-435. IEEE, (2014)