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Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures., , , , , , , , , and . VLSI Signal Processing, 9 (1-2): 49-65 (1995)System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs., , , and . VLSI Signal Processing, 18 (1): 39-50 (1998)Nonlinear transformations for high level regular array ASIC synthesis., , and . VLSI Signal Processing, 4 (4): 259-268 (1992)Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback., , , , and . DAC, page 327-332. ACM Press, (1999)Distributed Loop Controller for Multithreading in Unithreaded ILP Architectures., , , , and . IEEE Trans. Computers, 58 (3): 311-321 (2009)Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations., , , , and . ICICDT, page 1-4. IEEE, (2014)Accuracy of Quasi-Monte Carlo technique in failure probability estimations., , , , and . ICICDT, page 1-4. IEEE, (2016)Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (6): 1308-1321 (2019)Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 207-216 (2000)Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (1): 117-127 (2009)