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A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller.

, , , , , and . IEEE J. Solid State Circuits, 56 (2): 601-611 (2021)

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Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem., , , , and . PATMOS, page 56-63. IEEE, (2016)Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (2): 550-559 (2019)A Supply Voltage Control Method for Performance Guaranteed Ultra-Low-Power Microcontroller., , , , , and . IEEE J. Solid State Circuits, 56 (2): 601-611 (2021)A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator., , , , , and . IEEE J. Solid State Circuits, 51 (1): 31-44 (2016)Evaluation and analysis of single-phase clock flip-flops for NTV applications., , , , , and . PATMOS, page 1-6. IEEE, (2017)Unconventional Layout Techniques for a High Performance, Low Variability Subthreshold Standard Cell Library., , , and . ISVLSI, page 19-24. IEEE Computer Society, (2017)8.1 An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications., , , , , and . ISSCC, page 1-3. IEEE, (2015)A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy., , , and . ISLPED, page 1-6. IEEE, (2019)Pragmatic Memory-System Support for Intermittent Computing Using Emerging Nonvolatile Memory., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (1): 95-108 (2023)A Fokker-Planck Solver to Model MTJ Stochasticity., , and . ESSDERC, page 263-266. IEEE, (2021)