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Level C+ data reuse scheme for motion estimation with corresponding coding orders., , , и . IEEE Trans. Circuits Syst. Video Techn., 16 (4): 553-558 (2006)Partial-result-reuse architecture and its design technique for morphological operations with flat structuring elements., , и . IEEE Trans. Circuits Syst. Video Techn., 15 (9): 1156-1169 (2005)Fast disparity estimation algorithm for mesh-based stereo image/video compression with two-stage hybrid approach., , , , и . VCIP, том 5150 из Proceedings of SPIE, стр. 1521-1530. SPIE, (2003)Scalable module-based architecture for MPEG-4 BMA motion estimation., , , и . ISCAS (2), стр. 245-248. IEEE, (2001)Frame-level data reuse for motion-compensated temporal filtering., , , и . ISCAS, IEEE, (2006)A hardware accelerator for video segmentation using programmable morphology PE array., , и . ISCAS (4), стр. 341-344. IEEE, (2002)On-chip Principal Component Analysis with a Mean Pre-estimation Method for Spike Sorting., , , и . ISCAS, стр. 3110-3113. IEEE, (2009)128-channel Spike Sorting Processor with a Parallel-folding Structure in 90nm Process., , и . ISCAS, стр. 1253-1256. IEEE, (2009)Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT., , , , и . ISCAS (5), стр. 5190-5193. IEEE, (2005)Video Compression., и . Handbook of Signal Processing Systems, Springer, (2010)