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High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures.

, , and . FPL, page 1-4. IEEE, (2006)

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Enumeration of Costas Arrays Using GPUs and FPGAs., and . ReConFig, page 462-467. IEEE Computer Society, (2011)On the covering radius of some binary cyclic codes., , and . Adv. Math. Commun., 11 (2): 329-338 (2017)Multidimensional linear complexity analysis of periodic arrays., , , , , , and . Appl. Algebra Eng. Commun. Comput., 31 (1): 43-63 (2020)Modules to Teach Parallel and Distributed Computing Using MPI for Python and Disco., , and . IPDPS Workshops, page 958-962. IEEE Computer Society, (2016)High-Level Partitioning of Discrete Signal Transforms for Multi-FPGA Architectures., , and . FPL, page 1-4. IEEE, (2006)Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA Architectures., , and . FCCM, page 287-288. IEEE Computer Society, (2006)Reconfigurable Hardware Implementation of a Multivariate Polynomial Interpolation Algorithm., , and . Int. J. Reconfigurable Comput., (2010)A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks., , and . ReConFig, page 77-82. IEEE Computer Society, (2009)Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal Transforms., , and . ReConFig, page 103-108. IEEE Computer Society, (2008)A diagnostic method for detecting and assessing the impact of physical design optimizations on routing., , , and . ISPD, page 2-6. ACM, (2005)