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Disambiguation of "Yu, Shimeng"

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Device and System Level Design Considerations for Analog-Non-Volatile-Memory Based Neuromorphic Architectures.

, , , and . CoRR, (2015)

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Shimeng Chen

Yu-Ting Yu

Yu-Yu Su

Sze-Man Yu

Metal complexes with enolatoimine ligands for controlled olefin polymerizations. Uni Konstanz, (2009)

Zhejun Yu

 

Other publications of authors with the same name

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3067-3080 (2018)Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips., , , , , , , , , and 15 other author(s). IEEE J. Solid State Circuits, 57 (2): 609-624 (2022)ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (1): 353-363 (January 2023)Metal-Oxide RRAM., , , , , , , , and . Proc. IEEE, 100 (6): 1951-1970 (2012)Hardware-aware Quantization/Mapping Strategies for Compute-in-Memory Accelerators., , and . ACM Trans. Design Autom. Electr. Syst., 28 (3): 34:1-34:23 (2023)Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices., , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (4): 37:1-37:19 (2022)RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers., , and . DATE, page 1-6. IEEE, (2023)A Runtime Reconfigurable Design of Compute-in-Memory based Hardware Accelerator., , , , and . DATE, page 932-937. IEEE, (2021)Energy-Efficient Adaptive Computing With Multifunctional Memory., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (2): 191-195 (2017)Compute-in-Memory: From Device Innovation to 3D System Integration., , , , , , , and . ESSDERC, page 21-28. IEEE, (2021)