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Disambiguation of "Ishihara, Tohru"

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Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption.

, , and . PATMOS, volume 5349 of Lecture Notes in Computer Science, page 62-71. Springer, (2008)

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Tohru Iwai

Aeka Ishihara

Hirofumi Ishihara

 

Other publications of authors with the same name

Analytical Stability Modeling for CMOS Latches in Low Voltage Operation., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (12): 2463-2472 (2016)Message from the Editor-in-Chief.. IPSJ Trans. Syst. LSI Des. Methodol., (2024)Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring., , , and . IEEE J. Solid State Circuits, 50 (11): 2475-2490 (2015)Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure., , , and . PATMOS, page 237-242. IEEE, (2018)Microarchitectural-level statistical timing models for near-threshold circuit design., , and . ASP-DAC, page 87-93. IEEE, (2015)Power-Pro: Programmable Power Management Architecture., and . ASP-DAC, page 321-322. IEEE, (1998)Minimizing inter-task interferences in scratch-pad memory usage for reducing the energy consumption of multi-task systems., , , , and . CASES, page 157-166. ACM, (2010)Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing., , and . Integr., (2019)An energy-efficient on-chip memory structure for variability-aware near-threshold operation., , and . ISQED, page 23-28. IEEE, (2015)Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 107 (3): 540-548 (2024)