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Disambiguation of "Cheng, Ching-Hwa"

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A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.

, , , , and . ACM Trans. Design Autom. Electr. Syst., 14 (1): 17:1-17:17 (2009)

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Wei-Hwa Cheng

Ching-Cheng Hsu

Wilhelm Ching

Paisal Chingduang

Ching-Ching Pan

 

Other publications of authors with the same name

A panoramic endoscope design and implementation for Minimally Invasive Surgery., and . ISCAS, page 453-456. IEEE, (2014)Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing., , , and . ASP-DAC, page 367-368. IEEE, (2010)CKVdd: A Clock-Controlled Self-Stabilized Voltage Technique for Reducing Dynamic Power in CMOS Digital Circuits., and . IEICE Trans. Electron., 92-C (4): 391-400 (2009)Novel Techniques for Improving Testability Analysis., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A (12): 2901-2912 (2002)A hierarchy multiple-voltage design technique for low-power performance-manageable bio-chips., and . ICCE-TW, page 1-2. IEEE, (2016)Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing., , and . ITC, page 1. IEEE Computer Society, (2009)Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits., , , and . DFT, page 329-337. IEEE Computer Society, (2000)Built-in fine resolution clipping with calibration technique for high-speed testing by using wireless testers., and . DSN Workshops, page 81-84. IEEE Computer Society, (2011)Dual-phase pipeline circuit design automation with a built-in performance adjusting mechanism., , , , and . ASP-DAC, page 85-86. IEEE, (2011)Dynamic voltage domain assignment technique for low power performance manageable cell based design., , , and . ASP-DAC, page 359-360. IEEE, (2010)