( en | de | ru )

 

Disambiguation of "Zoni, Davide"

Author of the publication

copydeleteadd this publication to your clipboard
TEST: Assessing NoC Policies Facing Aging and Leakage Power.

, , , , and . DSD, page 606-613. IEEE Computer Society, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Vladimir Zonine

Ioannis Zonios

Davide Cadamuro

Davide Pennino

Davide Pagani

 

Other publications of authors with the same name

Thermal/performance trade-off in network-on-chip architectures., , and . ISSoC, page 1-8. IEEE, (2012)All-Digital Energy-Constrained Controller for General-Purpose Accelerators and CPUs., , and . IEEE Embed. Syst. Lett., 12 (1): 17-20 (2020)Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators., , , and . J. Syst. Archit., (2022)Exploring power reliability and performance aspects in on-chip networks for multi-cores.. Polytechnic University of Milan, Italy, (2014)A Low-Overhead Heuristic for Mixed Workload Resource Partitioning in Cluster-Based Architectures., , and . ARCS, volume 7179 of Lecture Notes in Computer Science, page 86-97. Springer, (2012)Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments., , , , , , , and . PARMA-DITAM, volume 107 of OASIcs, page 6:1-6:11. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2023)Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions., , , , and . ICECS, page 739-742. IEEE, (2019)BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers., , , , , and . J. Parallel Distributed Comput., (2017)Analysis and countermeasures to side-channel attacks: a hardware design perspective.. ReCoSoC, page 1-4. IEEE, (2019)A sensor-less NBTI mitigation methodology for NoC architectures., and . SoCC, page 340-345. IEEE, (2012)