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Disambiguation of "Nakajo, Hironori"

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A Packet Forwarding Layer for DIMMnet and its Hardware Implementation.

, , , , , and . PDPTA, page 461-467. CSREA Press, (2005)

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Hironori Kumeno

Hironori Tokuno

 

Other publications of authors with the same name

Implementation and Evaluation of a Thread Library for Multithreaded Architecture., , , , , , and . PDPTA, page 609-615. CSREA Press, (2003)Performance evaluation on low-latency communication mechanism of DIMMnet-2., , , , , and . Parallel and Distributed Computing and Networks, page 57-62. IASTED/ACTA Press, (2007)A memory accelerator with gather functions for bandwidth-bound irregular applications., , , , , , and . IA3@SC, page 35-42. ACM, (2011)Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2., , , , , , , and . ISHPC, volume 4759 of Lecture Notes in Computer Science, page 211-218. Springer, (2005)Operation in Partitioned Circuits with Scalable Hardware Mechanism., , , and . JCSSE, page 1-6. IEEE, (2018)A New Memory Module for Memory Intensive Applications., , , , , and . PARELEC, page 123-128. IEEE Computer Society, (2004)Overview of the JUMP-1, an MPP prototype for general-purpose parallel computations., , , , , , , , , and . ISPAN, page 427-434. IEEE Computer Society, (1994)Network Interface Architecture for Scalable Message Queue Processing., , , and . ICPADS, page 268-275. IEEE Computer Society, (2009)Parallelization of Recursive Function in Ruby-Based High-Level Synthesis., , and . FPT, page 407-410. IEEE, (2019)A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links., , and . Int. J. Parallel Program., 28 (2): 179-194 (2000)