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Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.

, , , , and . ESTIMedia, page 81-86. IEEE Computer Society, (2005)

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A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts., , , and . DAC, page 527-532. ACM Press, (1996)Effectiveness of the ASIP design system PEAS-III in design of pipelined processors., , , , , and . ASP-DAC, page 649-654. ACM, (2001)VLSI implementation of a real-time operating system., , , and . ASP-DAC, page 679-680. IEEE, (1997)A low-energy ASIP with flexible exponential Golomb codec for lossless data compression toward artificial vision systems., , , and . BioCAS, page 1-4. IEEE, (2015)A low power VLIW processor generation method by means of extracting non-redundant activation conditions., , , and . CODES+ISSS, page 227-232. ACM, (2007)Software Development Tool Generation Method Suitable for Instruction Set Extension of Embedded Processors., , , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)A Low-power ASIP Generation Method by Extracting Minimum Execution Conditions., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)Advantage and Possibility of Application-domain Specific Instruction-set Processor (ASIP)., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)Deformable Part Model Based Arrhythmia Detection Using Time Domain Features., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 100-A (11): 2221-2229 (2017)VLSI implementation and evaluation of a real-time operating system., , , , and . Syst. Comput. Jpn., 27 (6): 1-10 (1996)