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Parasitic Aware Routing Methodology Based on Higher Order RLCK Moment Metrics.

, and . VLSI Design, page 141-146. IEEE Computer Society, (2006)

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Dynamic Characteristics of Power Gating During Mode Transition., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (2): 237-249 (2011)Logic Encryption for Resource Constrained Designs., and . IEEE Access, (2021)Mitigating information leakage during critical communication using S*FSM., and . IET Comput. Digit. Tech., 13 (4): 292-301 (2019)Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis., , , , and . Formal Methods Syst. Des., 19 (3): 237-273 (2001)Finite state machine verification on MIMD machines., and . EURO-DAC, page 514-520. IEEE Computer Society Press, (1992)Interconnect Synthesis for Reconfigurable Multi-FPGA Architectures., , , and . IPPS/SPDP Workshops, volume 1586 of Lecture Notes in Computer Science, page 588-596. Springer, (1999)Scheduling for low power under resource and latency constraints., and . ISCAS, page 53-56. IEEE, (2000)Simulation based architectural power estimation for PLA-based controllers., and . ISLPED, page 121-124. IEEE, (1996)SoC Trust Validation Using Assertion-Based Security Monitors., , , and . ISQED, page 496-503. IEEE, (2021)Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks., , and . iSES, page 445-450. IEEE, (2022)