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Novel interconnect infrastructures for massive multicore chips - an overview., , , , and . ISCAS, page 2777-2780. IEEE, (2008)High-throughput, energy-efficient network-on-chip-based hardware accelerators., , and . Sustain. Comput. Informatics Syst., 3 (1): 36-46 (2013)Timing analysis of network on chip architectures for MP-SoC platforms., , , and . Microelectron. J., 36 (9): 833-845 (2005)A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With a Flying Capacitor Crossing Technique for Enhanced Power Efficiency., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (12): 2861-2871 (2019)Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (12): 2842-2854 (2019)Wireless NoC Platforms With Dynamic Task Allocation for Maximum Likelihood Phylogeny Reconstruction., , and . IEEE Des. Test, 31 (3): 54-64 (2014)Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies., and . IEEE Des. Test Comput., 27 (4): 6-9 (2010)Editorial.. IEEE Trans. Multi Scale Comput. Syst., 3 (2): 70-71 (2017)Editorial.. IEEE Trans. Multi Scale Comput. Syst., 2 (1): 1 (2016)Machine Learning and Manycore Systems Design: A Serendipitous Symbiosis., , , , and . Computer, 51 (7): 66-77 (2018)