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Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits., , and . ISCAS, page 435-438. IEEE, (1994)An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit Applications., and . Great Lakes Symposium on VLSI, page 68-. IEEE Computer Society, (1999)Maximum Current Estimation in Programmable Logic Arrays., and . Great Lakes Symposium on VLSI, page 301-306. IEEE Computer Society, (1998)Post-Route Gate Sizing for Crosstalk Noise Reduction., , , , , , and . ISQED, page 171-176. IEEE Computer Society, (2003)A Fast Coupling Aware Delay Estimation Scheme Based on Simplified Circuit Model., and . ISQED, page 133-138. IEEE Computer Society, (2001)An Analytical Model for Delay and Crosstalk Estimation with Application to Decoupling., and . ISQED, page 51-58. IEEE Computer Society, (2000)Computation of bus current variance for reliability estimation of VLSI circuits., , and . ICCAD, page 202-205. IEEE Computer Society, (1989)ACCORD: Automatic Catching and CORrection of Logic Design Errors in Combinatorial Circuits., and . ITC, page 742-751. IEEE Computer Society, (1992)Monte-Carlo approach for power estimation in sequential circuits., , and . ED&TC, page 416-420. IEEE Computer Society, (1997)An analytical model for delay and crosstalk estimation in interconnects under general switching conditions., and . ICECS, page 831-834. IEEE, (2000)