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Disambiguation of "Chen, Kun-Chih"

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Enabling fast preemption via Dual-Kernel support on GPUs.

, , , , and . ASP-DAC, page 121-126. IEEE, (2017)

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Kun Chen

Yung-chih Chen

Chih-Chun Chen

Chih-Hwa Chen

Chih-Chung Chen

 

Other publications of authors with the same name

Efficient pre-clipping and clipping algorithms for 3D graphics geometry computation., , , and . APCCAS, page 522-525. IEEE, (2008)Thermal-aware Dynamic Buffer Allocation for Proactive routing algorithm on 3D Network-on-Chip systems., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 10 (3): 376-387 (2020)Guest Editorial: Communication-Aware Designs and Methodologies for Reliable and Adaptable On-Chip AI SubSystems and Accelerators., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 10 (3): 265-267 (2020)Enabling fast preemption via Dual-Kernel support on GPUs., , , , and . ASP-DAC, page 121-126. IEEE, (2017)Dual-Precision Acceleration of Convolutional Neural Network Computation with Mixed Input and Output Data Reuse., , , and . ISCAS, page 1-4. IEEE, (2019)LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systems., , and . VLSI-DAT, page 1-4. IEEE, (2014)Traffic- and Thermal-aware Adaptive Beltway Routing for three dimensional Network-on-Chip systems., , , and . ISCAS, page 1660-1663. IEEE, (2013)Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method., , and . APCCAS, page 1079-1082. IEEE, (2010)An Overview of Efficient Interconnection Networks for Deep Neural Network Accelerators., , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 10 (3): 268-282 (2020)