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Disambiguation of "Sengupta, Anirban"

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Low-Cost Hardware Security of Laplace Edge Detection and Embossment Filter Using HLS Based Encryption and PSO.

, and . iSES, page 135-140. IEEE, (2023)

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Suprasanna Sengupta

Anirban Banerjee

Anirban Bhunia

Anirban Bhattacharyya

Anirban Chakraborty

 

Other publications of authors with the same name

Multi-phase watermark for IP core protection., and . ICCE, page 1-3. IEEE, (2018)Designing Low-Cost Hardware Accelerators for CE Devices Hardware Matters., , , and . IEEE Consumer Electronics Magazine, 6 (4): 140-149 (2017)User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis., and . ISQED, page 289-292. IEEE, (2015)Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper)., , and . Integr., (2017)Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors., and . Microelectron. Reliab., (2016)Robust Digital Signature to Protect IP Core against Fraudulent Ownership and Cloning., , and . ICCE-Berlin, page 1-3. IEEE, (2019)Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework., and . Security and Fault Tolerance in Internet of Things, Springer, (2019)Functional networks in non-human primate spinal cord and the effects of injury., , , , , , and . NeuroImage, (2021)Security of Functionally Obfuscated DSP Core Against Removal Attack Using SHA-512 Based Key Encryption Hardware., and . IEEE Access, (2019)Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS., and . Integr., (March 2024)