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A 101 dB SNDR 3.7mW switched-capacitor ΣΔ ADC using tri-level quantization., , , and . ASICON, page 40-43. IEEE, (2017)Half-Precision Logarithmic Arithmetic Unit Based on the Fused Logarithmic and Antilogarithmic Converter., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (2): 243-247 (2022)Fully Integrated Line Array Angular Displacement Sensing Chip., , , , , , , , and . Sensors, 23 (5): 2431 (March 2023)A 4MP high-dynamic-range, low-noise CMOS image sensor., , , , , and . IMSE, volume 9403 of SPIE Proceedings, page 940305. SPIE, (2015)A 14-bit 5 MS/s split non-binary SAR ADC., , , and . ASICON, page 765-768. IEEE, (2017)Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier., , , , and . IEEE J. Solid State Circuits, 45 (8): 1602-1614 (2010)NASH: Neural Architecture Search for Hardware-Optimized Machine Learning Models., , , and . CoRR, (2024)14-bit pipeline-SAR ADC for image sensor readout circuits., , , , , and . IMSE, volume 9403 of SPIE Proceedings, page 94030L. SPIE, (2015)A 600MS/s 30mW 0.13µm CMOS ADC array achieving over 60dB SFDR with adaptive digital equalization., , , , , , , , and . ISSCC, page 82-83. IEEE, (2009)A Single Photon Detector Readout Circuit Based on 0.18 μm CMOS Technology., , , , and . ASICON, page 1-4. IEEE, (2021)