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Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates.

Y. Zhang, H. Lv, H. Du, C. Huang, S. Liu, and G. Xie. Int. J. Circuit Theory Appl., 44 (7): 1351-1366 (2016)

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Jian Xie

Yangpei Xie

Mingliang Xie

Qian Xie

Zhenwei Xie

Other publications of authors with the same name

Design of a Stochastic Computing Architecture for the Phansalkar Algorithm.Y. Zhang, J. Qin, J. Han, and G. Xie. IEEE Trans. Very Large Scale Integr. Syst., 32 (3): 442-454 (March 2024)A novel control circuit for piezoelectric energy harvesting.Z. Zhang, Z. Tang, Z. Yunfeng, X. Cheng, and G. Xie. Microelectron. J., (2021)Using correction parameters to improve real-time video interpolation in low-cost VLSI implementation.H. Guan, Z. Zhang, X. Cheng, Y. Yang, and G. Xie. Microelectron. J., (2021)A 15 W wireless power receiver with an improved full-wave synchronous rectifier.C. Wu, G. Xie, Z. Zhang, X. Cheng, T. Fei, J. Zeng, and X. Zeng. IEICE Electron. Express, 15 (20): 20180732 (2018)DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing.J. Zeng, Z. Zhang, R. Chen, S. Liang, T. Cao, Z. Yu, X. Cheng, and G. Xie. IEICE Electron. Express, 17 (4): 20200005 (2020)Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata.Y. Zhang, C. Zhu, X. Cheng, and G. Xie. IEEE Trans. Circuits Syst. II Express Briefs, 69 (9): 3909-3913 (2022)A 30MHz Delay-Line-Based Buck Converter with 5.7%-94.8% Switching Duty Cycle.Z. Zhang, S. Xu, F. Yao, G. Xie, and X. Cheng. APCCAS, page 53-56. IEEE, (2019)End-to-End Background Subtraction via a Multi-Scale Spatio-Temporal Model.Y. Yang, T. Zhang, J. Hu, D. Xu, and G. Xie. IEEE Access, (2019)Module-based design method using clocking scheme for quantum-dot cellular automata.F. Deng, G. Xie, Y. Zhang, and S. Chen. Int. J. Circuit Theory Appl., 50 (2): 448-464 (2022)A stochastic computing architecture for local contrast and mean image thresholding algorithm.W. Xu, G. Xie, S. Wang, Z. Lin, J. Han, and Y. Zhang. Int. J. Circuit Theory Appl., 50 (9): 3279-3291 (2022)

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Disambiguation of "Xie, Guangjun"

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Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates.

Please choose a person to relate this publication to

Jian Xie

Yangpei Xie

Mingliang Xie

Qian Xie

Zhenwei Xie

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Xie, Guangjun"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates.

Please choose a person to relate this publication to

Jian Xie

Yangpei Xie

Mingliang Xie

Qian Xie

Zhenwei Xie

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Modular design of QCA carry flow adders and multiplier with reduced wire crossing and number of logic gates.