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Disambiguation of "Marinissen, Erik Jan"

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Contactless testing: Possibility or pipe-dream?

, , , , , , and . DATE, page 676-681. IEEE, (2009)

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Jan-Erik Schmutz

Adhäsions- und Abriebuntersuchungen mittels rasterkraftmikroskopischer Techniken auf der Mikro- und Nanoskala. Uni Münster, (2009)

Nilgün Erikli

Anders Erikson

Jan Erik Spitzley

Jan Erik Eickbohm

 

Other publications of authors with the same name

An Industrial Approach to Core-Based System Chip Testing.. VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 389-400. Kluwer, (2001)How Useful are the ITC 02 SoC Test Benchmarks?, and . IEEE Des. Test Comput., 19 (5): 120, 119 (2002)SOC test architecture design for efficient utilization of test bandwidth., and . ACM Trans. Design Autom. Electr. Syst., 8 (4): 399-429 (2003)Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis., and . IEEE Des. Test Comput., 25 (3): 206-207 (2008)Conference Reports., , , , , and . IEEE Des. Test Comput., 23 (4): 262-265 (2006)Device-Aware Test for Back-Hopping Defects in STT-MRAMs., , , , , , , , and . DATE, page 1-6. IEEE, (2023)Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs., , , , , and . ITC, page 1-10. IEEE, (2020)Process Complexity and Cost Considerations of Multi-Layer Die Stacks., , , , , , , , , and 5 other author(s). 3DIC, page 1-6. IEEE, (2019)Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs.. DATE, page 1277-1282. IEEE, (2012)Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization., and . DATE, page 10738-10741. IEEE Computer Society, (2003)