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Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management.

, , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5142-5155 (2020)

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Exploring the limits of Concurrency in ML Training on Google TPUs., , , , , , , , , and 9 other author(s). CoRR, (2020)Voltage-Stacked GPUs: A Control Theory Driven Cross-Layer Solution for Practical Voltage Stacking in GPUs., , , , , , and . MICRO, page 390-402. IEEE Computer Society, (2018)Ti-States: Power Management in Active Timing Margin Processors., , , and . IEEE Micro, 37 (3): 106-114 (2017)Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (1): 171-184 (2021)Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (12): 5142-5155 (2020)An Efficient Power-Aware Resource Scheduling Strategy in Virtualized Datacenters., , and . ICPADS, page 110-117. IEEE Computer Society, (2013)Ti-states: Processor power management in the temperature inversion region., , , and . MICRO, page 55:1-55:13. IEEE Computer Society, (2016)Flying IoT: Toward Low-Power Vision in the Sky., , , , and . IEEE Micro, 37 (6): 40-51 (2017)GPUVolt: modeling and characterizing voltage noise in GPU architectures., , , , and . ISLPED, page 141-146. ACM, (2014)Erratum to "Predictive Guardbanding: Program-Driven Timing Margin Reduction for GPUs"., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (6): 1272 (2021)