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P.SIZE: a sizing aid for optimized designs., , and . EURO-DAC, page 160-165. IEEE Computer Society Press, (1992)Second Generation Delay Model for Submicron CMOS Process., , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 159-167. Springer, (2000)Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design., , and . PATMOS, volume 1918 of Lecture Notes in Computer Science, page 129-138. Springer, (2000)Delay bound based CMOS gate sizing technique., , , , and . ISCAS (5), page 189-192. IEEE, (2004)A novel macromodel for power estimation in CMOS structures., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (11): 1090-1098 (1998)Delay modelling improvement for low voltage applications., , and . EURO-DAC, page 216-221. IEEE Computer Society, (1995)Design Techniques for EEPROMs Embedded in Portable Systems on Chips., , , , , , and . IEEE Des. Test Comput., 20 (1): 68-75 (2003)Transition time modeling in deep submicron CMOS., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (11): 1352-1363 (2002)Delay bound determination for timing closure satisfaction., , and . ISCAS (5), page 375-378. IEEE, (2001)Temperature Dependence in Low Power CMOS UDSM Process., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 110-118. Springer, (2004)