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A distributed processor state management architecture for large-window processors.

, , , , , and . MICRO, page 11-22. IEEE Computer Society, (2008)

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A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)Picos: A hardware runtime architecture support for OmpSs., , , , and . Future Gener. Comput. Syst., (2015)Thread Lock Section-Aware Scheduling on Asymmetric Single-ISA Multi-Core., , , , and . IEEE Comput. Archit. Lett., 14 (2): 160-163 (2015)Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures., , , and . Int. J. Parallel Program., 32 (6): 447-474 (2004)Hybrid Transactional Memory with Pessimistic Concurrency Control., , , , , , , and . Int. J. Parallel Program., 39 (3): 375-396 (2011)RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only)., , , , , and . SIGMETRICS Perform. Evaluation Rev., 39 (3): 19 (2011)Dynamic Cache Partitioning Based on the MLP of Cache Misses., , , and . Trans. High Perform. Embed. Archit. Compil., (2011)Memory Access Synchronization in Vector Multiprocessors., , and . CONPAR, volume 854 of Lecture Notes in Computer Science, page 414-425. Springer, (1994)Topic 15+20: Multimedia and Embedded Systems., , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 651-652. Springer, (2001)